The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of preventing breakdown of a gate oxide film of a MOS field effect transistor.
In the semiconductor integrated circuit, a gate voltage of a MOS field effect transistor is clamped at a power voltage level or the ground level. If the gate of the MOS field effect transistor is directly connected to a power source or a ground line, then static electricity or noises apply a voltage directly to the gate of the MOS field effect transistor whereby breakdown of a gate insulation film of the MOS field effect transistor may appear.
FIG. 1 is a view illustrative of the conventional semiconductor integrated circuit including a plurality of logic circuits D1-Dn and a plurality of circuits E1-Em. FIG. 2 is a circuit diagram of each of the logic circuits D1-Dn. Each logic circuit has a p-channel MOS field effect transistor T1 with a gate which is connected through a resistance 71 to the ground line. The p-channel MOS field effect transistor T1 is kept in ON state. Each logic circuit also has an n-channel MOS field effect transistor T2 with a gate which is connected through a resistance 72 to a high voltage line Vcc whereby the n-channel MOS field effect transistor T2 is kept in ON state. Each logic circuit also has a p-channel MOS field effect transistor T3 with a gate connected to a first terminal C1. Each logic circuit also has an n-channel MOS field effect transistor T4 with a gate connected to the first terminal C1 so that the gate of the n-channel MOS field effect transistor T4 has the same potential as the voltage of the gate of the p-channel MOS field effect transistor T3. Each logic circuit also has a p-channel MOS field effect transistor T5 with a gate connected to a third terminal C3. Each logic circuit also has an n-channel MOS field effect transistor T6 with a gate connected to the third terminal C3 so that the gate of the n-channel MOS field effect transistor T6 has the same potential as the voltage of the gate of the p-channel MOS field effect transistor T5. Each logic circuit also has an n-channel MOS field effect transistor T8. A gate of the n-channel MOS field effect transistor T8 is connected to an output terminal of an invertor 3. A drain of the n-channel MOS field effect transistor T8 is connected to a drain of the n-channel MOS field effect transistor T4. A source of the n-channel MOS field effect transistor T8 is connected to a drain of an n-channel MOS field effect transistor T9. The invertor 3 has an input terminal connected to a second terminal C2. A gate of the n-channel MOS field effect transistor T9 is connected to the third terminal C3 so that the gate of the n-channel MOS field effect transistor T9 has the same potential as the gate of the n-channel MOS field effect transistor T6.
The following description will focus on operations of the above individual integrated circuit. The description will be made with reference to FIG. 2. The p-channel MOS field effect transistor T1 is kept in ON state since the gate of the p-channel MOS field effect transistor T1 is connected through the resistance 71 to the ground line. The n-channel MOS field effect transistor T2 is kept in ON state since the gate of the n-channel MOS field effect transistor T2 is connected through the resistance 72 to the high voltage line Vcc. The n-channel and p-channel MOS field effect transistors T1 and T2 provide no effect to the operations of the integrated circuit.
When a first input signal to be applied to the first terminal C1 is high level, then the p-channel MOS field effect transistor T3 turns OFF whilst the n-channel MOS field effect transistor T4 turns ON whereby an output terminal C4 is conductive to the ground line. As a result, a low level output signal appears on the output terminal C4 regardless of second and third input signals to be inputted into the second and third input terminals C2 and C3.
Also if a third input signal to be applied to the third terminal C3 is high level, then the p-channel MOS field effect transistor T5 turns OFF whilst the n-channel MOS field effect transistor T6 turns ON and also the n-channel MOS field effect transistor T6 is kept in ON state whereby the output terminal C4 is conductive to the ground line. As a result, a low level output signal appears on the output terminal C4 regardless of the first and second input signals to be inputted into the first and second input terminals C1 and C2.
If the first and third input signals to be inputted into the first and third input terminals are the low level, then the p-channel MOS field effect transistor T1 is kept in ON state and the p-channel MOS field effect transistors T3 and T5 turn ON whilst the n-channel MOS field effect transistors T4 and T6 turn OFF whereby the output terminal C4 is conductive to the high voltage line Vcc. As a result, the high level signal appears on the output terminal C4.
From the above descriptions, the integrated circuits D1-Dn are two-input OR gates.
If the second input signal to be inputted into the second input terminal is high level, then an output signal from the invertor 3 is low level whereby the n-channel MOS field effect transistor T8 turns OFF. As a result, ON/OFF operations of the n-channel MOS field effect transistor T9 provide no effect to the operations of the integrated circuit.
If the second input signal to be inputted into the second input terminal C2 is low level whilst the third input signal to be inputted into the third input terminal C3 is high level, then the n-channel MOS field effect transistors T6 and T9 turn ON concurrently whereby the majority of the current flows through the n-channel MOS field effect transistor T6. Namely, if the second input signal to be inputted into the second input terminal C2 is low level, then a logic threshold voltage of the OR gate is dropped where the logic threshold voltage is a threshold voltage of whether the OR gate turns ON or OFF by the third input signal inputted into the third input signal terminal C3.
The following descriptions will focus on the integrated circuits E1-Em. The descriptions will be made with reference to FIG. 3. Each of the integrated circuits E1-Em has an input terminal C5 and an output terminal C6 and also is supplied with a power through a high voltage line Vcc. Each logic circuit has an invertor 6 with an output terminal connected to the output terminal C6. Each logic circuit has an EXOR gate 5 with an output terminal connected to an input terminal of the invertor 6. The input terminal C5 is connected to one of input terminals of the EXOR gate 5. Each logic circuit has an invertor 4 with an output terminal connected to the other one of the input terminals of the EXOR gate 5. An input terminal of the invertor 4 is connected through a resistance 73 to the high voltage line Vcc. The invertor 4 has MOS field effect transistors. The resistance 73 prevents the gate breakdown of the MOS field effect transistors in the invertor 4.
The following descriptions will focus on the operations of the above integrated circuits E1-Em. Since the input terminal of the invertor 4 is connected through the resistance 73 to the high voltage line Vcc, then the output signal from the invertor 4 is kept in low level. The output signal from the invertor 4 is inputted into the one input terminal of the EXOR gate 5. As a result, the one input terminal of the EXOR gate 5 is kept to receive the low level signal, for which reason the output signal from the EXOR gate 5 depends upon the signal inputted to the input terminal C5. Namely, if the input signal inputted through the input terminal C5 is low level, then the output signal from the EXOR gate 5 is high level. If, however, the input signal inputted through the input terminal C5 is low level, then the output signal from the EXOR gate 5 is high level. The output terminal of the EXOR gate 5 is connected through the invertor 6 to the output terminal C6. Therefore, if the input signal inputted through the input terminal C5 is low level, the low level output signal appears on the output terminal C6. If, however, the input signal inputted through the input terminal C5 is high level, the high level output signal appears on the output terminal C6. Namely, the integrated circuits E1-Em serve as buffer circuits.
As described above, the resistances 71, 72 and 73 serve to prevent the gate breakdown. The circuits D1-Dn have 2n of the resistances whilst the circuits E1-Em have m of the resistances. In order to form the resistance of 1 k.OMEGA., 2070 .mu.m.sup.2 is necessary in case of diffusion resistance or 870 .mu.m.sup.2 is necessary in case of polysilicon resistance.
As the scale of the semiconductor integrated circuits will become large in future, the number of the MOS field effect transistors used is increased whereby the necessary area for placing the resistances is also increased. This results in the increase in area of the semiconductor chip.
Under the above circumstances, it had been required to develop the semiconductor integrated circuits capable of preventing the gate breakdown without any substantive increase in area for placement of the resistances on the semiconductor chip.